NMOS transistors are widely used in integrated circuit applications. One application is in a programmable logic device (PLD), such as a field programmable gate array where voltage passes through an NMOS transistor to erase a flash memory cell. Flash memory cells are erased by gradually applying an erasing voltage to an erase pin on the memory cell.
A drawback to using an NMOS transistor to supply an erasing voltage to a memory cell is that an NMOS transistor does not provide the full input voltage to the memory cell and thus does not "efficiently" erase the memory cell. As is known in the art, the efficiency of a memory cell erasure is defined in terms of a subsequent voltage on the gate of the memory cell required to read the cell. The more efficiently a memory cell is erased, the lower a voltage required to read the memory cell. The less efficiently a memory cell is erased, the higher a voltage required to read the memory cell. The NMOS transistor does not provide the full input voltage to the memory cell, partly because of a "body effect" voltage loss that it experiences. The body effect voltage loss of NMOS transistors is discussed in "Principles of CMOS VLSI Design," by Weste and Eshraghian .COPYRGT.1985, pp. 38-39.
As an example, if a flash memory cell requires 12V at its erase pin for the memory cell to be efficiently erased, then an NMOS transistor receiving an erasing voltage of 12V would be inadequate, since typically the total threhold voltage loss NMOS transistor would limit the voltage seen at the erase pin of the memory cell to only 10.5V.
There have been two main approaches for overcoming the voltage loss of NMOS transistors. A first approach has been to increase the erasing voltage applied to the input of the NMOS transistor. Increasing the erasing voltage, however, increases the chances of dielectric breakdown within the NMOS integrated circuit. While integrated circuit manufacturers could enhance their fabrication processes to reduce the possibility of dielectric breakdown, to do so would increase the price of an integrated circuit.
A second approach has been to replace the NMOS transistor with a PMOS transistor. A PMOS transistor typically does not suffer voltage loss at higher voltages since its source and body are electrically coupled. However, a PMOS transistor unfortunately does not lend itself to controlled and gradual ramping of its output voltage in response to a gradual ramping of its gate voltage. In fact, a PMOS transistor is almost totally off until its gate voltage reaches its threshold voltage, and thereafter is fully on.
What is needed is a circuit that overcomes the voltage loss in an NMOS transistor and which addresses the limitations of the prior art described above.